Many power-efficient circuit designs today have multiple voltage domains. Device electrical overstress occurs when a low-voltage device is driven by a high-voltage power rail, signal, or bulk connection with the potential to cause long-term or permanent damage (usually in the form of oxide breakdown). This damage results in circuit degradation or failure over time. Conversely, when insufficient voltage is applied to a high-voltage device or the device is driven by a low-voltage net, the device may not switch, or may switch slowly, again degrading circuit performance.
Thin-oxide transistors, used extensively at advanced nodes, are less robust against electrical failure and impose new electrical overstress verification challenges. Thinner oxide generally allows for the use of lower voltage and provides less power. When power domain design errors occur, effects such as negative bias temperature instability (NBTI) can lead to the threshold voltage of the PMOS transistors increasing over time, resulting in reduced switching speeds for logic gates, and hot carrier injection (HCI) issues, altering the threshold voltage of NMOS devices over time. Soft breakdown (SBD), as a time-dependent failure mechanism, also contributes to the degradation effects of gate oxide breakdown.
Electrical overstress is an important concern for both analog and digital designers, due to the variety of power conditions commonly used in all designs, such as multiple power domains, standby/wake-up/low power/power-down conditions (in which there is no bias current, but the battery is present), and the presence of high-voltage signals. Understanding device pin voltages in all modes of operation is thus critical for detecting potential electrical overstress issues. The ability to identify device breakdown, recognize reverse breakdown issues in high-voltage areas, and detect maximum voltage across gate oxides are all part of a robust electrical overstress detection strategy.
Verifying device operating voltage conditions in voltage-controlled designs, however, is very complicated. Achieving this with exhaustive dynamic simulation is simply not practical at the full chip level due to the turnaround time involved. If the design is a large system-on-chip design, it may not even be possible to simulate it in its entirety. Many design teams employ SPICE (Simulation Program with Integrated Circuit Emphasis) simulations and user-generated marker layers or text points to check for electrical overstress, but this is an error-prone method because it requires the designer to manually determine how voltages propagate throughout the design, and manually mark the correct regions for high-voltage design rules. Markers are also extremely difficult to maintain as the design is changed and can miss errors due to lack of simulation coverage.
With consumer expectations for longer device operation at sustained performance levels, designing for reliability is no longer an optional product feature, but a necessary and integral part of a product's specifications. Designers need verification tools and techniques that go beyond the traditional triumvirate of design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC) to provide thorough detection of and protection against electrical overstress conditions.